Adalberto Claudio Quiros

PhD Candidate at University of Glasgow

About Me

I’m a third year PhD student advised by Ke Yuan and Roderick Murray-Smith at the Univeristy of Glasgow, Computing Science department.

I’m interested in generative models, causal inference, representation learning (unsupervised and self-supervised), and interpretability of latent variable models. Additionally, my current research focuses on applying generative models to histopathology and how these models can help to better understand cancer tissue.

On a personal level, I’m interested in U.S., U.K. and E.U. politics, politcal/social science and their intersection with machine learning.

Before starting the PhD, I worked in the semiconductor industry as a SoC Design engineer in the FPGA field at Altera Coporation and Intel Corporation in San Jose, CA. I received an M.S. in Electrical Engineering at the IIT in Chicago, and M.S. and B.S. degrees in Telecommunications Engineering at ETSIT-UPM in Madrid.

Research Experience

Preprints

'Learning a low dimensional manifold of real cancer tissue with Pathology GAN' Adalberto Claudio Quiros, Roderick Murray-Smith, Ke Yuan. 2020.

http://arxiv.org/abs/2004.06517

NeurIPS 2020 Learning Meaningful Representations of Life Workshop.
Late breaking research talk at RECOMB 2020 Computational Cancer Biology.

Abstract: Application of deep learning in digital pathology shows promise on improving disease diagnosis and understanding. We present a deep generative model that learns to simulate high-fidelity cancer tissue images while mapping the real images onto an interpretable low dimensional latent space. The key to the model is an encoder trained by a previously developed generative adversarial network, PathologyGAN. We study the latent space using 249K images from two breast cancer cohorts. We find that the latent space encodes morphological characteristics of tissues (e.g. patterns of cancer, lymphocytes, and stromal cells). In addition, the latent space reveals distinctly enriched clusters of tissue architectures in the high-risk patient group. hand

Publications

'Pathology GAN: Learning deep representations of cancer tissue' Adalberto Claudio Quiros, Roderick Murray-Smith, Ke Yuan. 2020.

http://proceedings.mlr.press/v121/quiros20a.html

Proceedings of the Third Conference on Medical Imaging with Deep Learning, PMLR, 2020

tran Abstract: We apply Generative Adversarial Networks (GANs) to the domain of digital pathology. Current machine learning research for digital pathology focuses on diagnosis, but we suggest a different approach and advocate that generative models could drive forward the understanding of morphological characteristics of cancer tissue. In this paper, we develop a framework which allows GANs to capture key tissue features and uses these characteristics to give structure to its latent space. To this end, we trained our model on 249K H&E breast cancer tissue images. We show that our model generates high quality images, with a Frechet Inception Distance (FID) of 16.65. We additionally assess the quality of the images with cancer tissue characteristics (e.g. count of cancer, lymphocytes, or stromal cells), using quantitative information to calculate the FID and showing consistent performance of 9.86. Additionally, the latent space of our model shows an interpretable structure and allows semantic vector operations that translate into tissue feature transformations. Furthermore, ratings from two expert pathologists found no significant difference between our generated tissue images from real ones. hand

'DNNLibGen : Deep Neural Network Based Fast Library Generator' Eunice Naswali, Adalberto Claudio Quiros, Pravin Chandran. 2019.

https://ieeexplore.ieee.org/document/8965191

26th IEEE International Conference on Electronics Circuits and Systems

tran Abstract: We propose a new modeling methodology using deep learning techniques for generating timing models for Static Timing Analysis (STA). Current device behavior is non-linear, non-monotonic and exhibits high sensitivity to (Process Voltage Temperature) PVT variation which imposes a myriad of design challenges including the need for analysis at several PVT corners. While complete PVT coverage is crucial for detecting design issues early and achieving time-to-market goals with improved predictability, the number of PVT corners are growing exponentially and library generation has also become a significant bottleneck in current design cycles. To this end, we have developed a novel methodology for timing library generation that uses data from sparse characterization in PVT space and generates delay models at required sign-off corners. We have employed deep neural nets with residual connections for delay modeling and our methodology enables a ‘single model’ to fully comprehend multiple cell types, PVT corners and generate required PVT timing libraries. The proposed library-generator uses a novel inter-corner model to generate delay tables at 17 test corners using 7 corners as reference. In addition, we have developed an intra-corner model, to generate dense 8x8 delay tables using delays from 10 slew/load points as reference. The results show that, using these models, we are able to achieve key improvements with over 98.7% of calculated delays within acceptable tolerance while reducing characterization run-time for early milestones by up to 60%.

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Miscellaneous

Professional Experience

Intel Corporation

San Jose, CA, USA

Senior SoC Design Engineer - Fabric Performance Leadership Team

April 2017 – September 2018

I worked in the Fabric Performance Leadership team, our goal was to analyze the Stratix 10 FPGA design from the hardware and software perspective to find flaws and push the FPGA frequency performance forward.

During this period, a few of the most important achievements were:

  • A Python graph builder tool that generates a graph of the FPGA’s routing structure, prunes it and creates a visualization from an register-transfer level netlist design.
  • Implementated a device End-of-Life (EOL) methodology tool that obtained the aging degradation delay on FPGA’s transistors.
  • Analyzed logical and physical implementation of Adders: From the FPGA software, integrated circuit design and architecture perspective. The result of this study was a redesign of the adder’s implementation leading to a 70% improvement on frequency performance for adders.
  • Published ‘DNNLibGen : Deep Neural Network Based Fast Library Generator’ Eunice Naswali, Adalberto Claudio Quiros, Pravin Chandran.

Altera Coporation/Intel Corporation

San Jose, CA, USA

Senior SoC Design Engineer - Full Chip Timing Team

June 2014 – April 2017

Worked in the Full Chip Timing team on Static Timing Analysis, first to verify the hardware FPGA designs running at the frequency specifications, and secondly to correlate the FPGA software models with the hardware designs and silicon devices.

  • Developed a Stratix 10 full chip timing violation tool: This tool gathers all full chip timing violations due to maximum transition (~100K instances), cross reference each violation to a lower system blocks, and compiles them for each block designer.
  • Arria 10 Frequency binning and register to register timing correlation lead: Silicon/Quartus-FPGA-SW/HSPICE model frequency correlation, given an internal Altera Quality Award in 2015 Q2.
  • Developed a timing tool in Python, HSPICE, and Quartus FPGA Software significantly impacting the process: Increasing the number of data points from 10 to 7K, with different features including Power-Voltage-Temperature (PVT), voltage threshold and sheet resistance sweeping options.

Channel IQ - Currently Market Track

Chicago IL, USA

Data Acquistion Engineer

August 2013 – June 2014

Worked developing bots for web data scraping, additionally I help in maintaining and developing improvements on middle tier code and servers, which controled the bots and jobs executions. Most of this work was done in SQL, C#, Python, C++.

Education

Illinois Institute of Technology

Master of Science in Electrical Engineering - 3.53/4

Chicago, IL, USA

Polytechnic University of Madrid, ESTIT-UPM

Master & Bachelor of Science in Telecommunications Engineering - 7.23/10

Madrid, Spain